Patents
Word-line biasing in memory arrays of core flash memory chips for faster speeds and lower power consumption, US10325667B2, Link
Address decoding architecture to reduce area and improve speeds of core flash memory chips, US10325656B2, Link
Physical layout of high-voltage transistors for flash memory chips for faster performance, US9773555B2, Link
Word-line biasing in memory arrays at the core of flash memory chips for faster performance, US9767908B2, Link
Programming order of Word-lines in memory arrays of flash memory chips to reduce disturbs, US9767910B1, Link
Low-voltage block decoder circuit for core flash memory chips to reduce area, US9786377, Link
Stress relief for high-voltage level shifters for core flash memory chips, US9953715B2, Link
Under Construction
Publications
“A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology”, IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018.
“All-digital Wireless Transceiver With Sub-sampling Demodulation and Burst-Error Correction,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2012.
“All-digital 400~900 MHz Power Amplifier Consuming 0.03 mW/MHz Using 0.18 um CMOS,” IEEE Intl. Conf. on Electronic Circuits and Systems, 2011.
“All digital wireless transceiver using modified BPSK and 2/3 sub-sampling technique,” Proc. IEEE Application Specific Integrated Circuits Conf., 2009. (Best student paper award)
“All digital baseband 50 Mbps data recovery using 5x oversampling with 0.9 data unit interval clock jitter tolerance,” Proc. IEEE Symp. on Design and Diagnostics of Electronic Circuits and Systems, 2009.